A variety of battery powered portable devices, such as mobile phones, notebook computers and the like, have become popular. Each portable device may employ a plurality of integrated circuits. In order to extend the battery life of portable devices, power dissipation of integrated circuits has become a major concern. Various power saving solutions have been adopted to improve the power dissipation of a portable device. Among them, reducing clock network power dissipation is an effective way to reduce the total power consumption in modern portable devices comprising a plurality of high performance digital systems.
A digital system may comprise various synchronous circuits, which need a clock to synchronize all parts together. As semiconductor technologies further advance, the frequency of clock signals increases as well. As a result, the power consumption of the clock network increases accordingly. Internal clock gating is an effective technique to reduce the total clock network power dissipation of a battery powered digital system. More particularly, the internal clock gating technique disables the clock of some circuits of the digital system when they are not in use during some particular clock cycles. By shutting down the clock of inactive circuits, the internal clock gating technique can prevent the inactive circuits from consuming unnecessary power so as to extend the battery life of a battery powered digital system.
Internal clock gating may be implemented by employing at least a latch such as a positive edge triggered D type flip-flop. However, a latch circuit may result in two types of delays, namely propagation delay and setup and hold time delay. The propagation delay of digital circuits is defined as the amount of time between a change in an input and a change on the output. The change is specified as a 50% point on the input signal to a 50% point on the output signal. The propagation delay is related to the switching time of transistors within a logic gate. In a latch circuit, the major delay source is a CP-to-Q delay, which is defined as the amount of delay time between the change of the clock signal of the latch and the corresponding change in the output signal Q.
On the other hand, the setup time is defined as a minimum period in which a data signal is held steady before the leading edge of a clock signal is applied to the D type flip-flop. A valid and constant data signal during such a period can prevent the flip-flop from entering a metastable state in which the output of the D type flip-flop is not predictable. Furthermore, the output of the D type flip-flop may oscillate between a logic low state and a logic high state. Likewise, the hold time is defined as a period after the leading edge of the clock signal. Similarly, during the specified hold time, the data signal must be kept valid and constant so that the flip-flop can generate a valid output. The setup and hold time of synchronous circuits may vary based upon different semiconductor processes. A typical setup and hold time may be less than one hundred picoseconds.
As modern computing power advances and core processors may operate in the order of GHz, the delay time from internal clock gating may have a negative impact on the performance of core processor units. Furthermore, the long delay time may prevent a core processor unit from achieving high performance by further increasing its operating frequency. Moreover, at a high operating frequency, in order to reduce the total power dissipation, reducing the unnecessary power losses by employing internal clock gating is a necessary step to extend battery life.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.